A 372 ps 64-bit adder using fast pull-up logic in 0.18µm CMOS
نویسندگان
چکیده
This paper presents a 372ps 64-bit adder using Fast Pull-up Logic (FPL) in 0.18 μm CMOS technology. Fast Pullup Logic is devised and applied to decrease pull-up time which is critical in domino-static adder. The implemented adder measures the worst case delay of 372ps. The adder has a modified tree architecture using Load Distribution Method and has 6 logic stages.
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